Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells
US9985042B2 · kind B2 · utility
8Cited by
6References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 17, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | May 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.