Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device
US9991352B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2017 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Jul 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.