Three-dimensional semiconductor device and method of fabrication
US9997598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2017 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Aug 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.