John Liberty
27Patents
8h-index
29Co-inventors
75Inventor score
Filing activity: May 11, 1989 → Feb 19, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6421053B1 | Block rendering method for a graphics subsystem | Physics | 36 | Expired |
| US6760819B2 | Symmetric multiprocessor coherence mechanism | Physics | 29 | Expired |
| US7496692B2 | Validating chip configuration data | Physics | 27 | Active |
| US5432865A | Method and apparatus for generating a plurality of parameters of an object in a field of view | Physics | 24 | Expired |
| US7043579B2 | Ring-topology based multiprocessor data access bus | Physics | 21 | Expired |
| US7533238B2 | Method for limiting the size of a local storage of a processor | Physics | 13 | Active |
| US5121436A | Method and apparatus for generating a plurality of parameters of an object in a field of view | Physics | 12 | Expired |
| US7197655B2 | Lowered PU power usage method and apparatus | Physics | 8 | Expired |
| US7500039B2 | Method for communicating with a processor event facility | Physics | 6 | Active |
| US7869459B2 | Communicating instructions and data between a processor and external devices | Electricity | 5 | Active |
| US7233212B2 | Oscillator array with row and column control | Electricity | 5 | Expired |
| US7778271B2 | Method for communicating instructions and data between a processor and external devices | Electricity | 5 | Active |
| US8838950B2 | Security architecture for system on chip | Electricity | 4 | Active |
| US7986330B2 | Method and apparatus for generating gammacorrected antialiased lines | Physics | 4 | Active |
| US7279996B2 | Method of functionality testing for a ring oscillator | Electricity | 4 | Expired |
| US7890561B2 | Random number generator | Electricity | 3 | Active |
| US8918442B2 | Reducing bias in hardware generated random numbers | Physics | 3 | Active |
| US8230495B2 | Method for security in electronically fused encryption keys | Electricity | 2 | Active |
| US7870308B2 | Programmable direct memory access engine | Physics | 1 | Active |
| US7930457B2 | Channel mechanisms for communicating with a processor event facility | Physics | 1 | Active |
| US7870309B2 | Multithreaded programmable direct memory access engine | Physics | 1 | Active |
| US7730279B2 | System for limiting the size of a local storage of a processor | Physics | 0 | Active |
| US8918553B2 | Multithreaded programmable direct memory access engine | Physics | 0 | Active |
| US11372703B1 | Reduced system memory latency via a variable latency interface | Physics | 0 | Active |
| US8918443B2 | Reducing bias in hardware generated random numbers | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.