Instruction and logic for optimization level aware branch prediction
US10157063B2 · kind B2 · utility
0Cited by
2References
6Claims
0Family size
Assignee
Inventors
- Polychronis Xekalakis
- Pedro Marcuello
- Alejandro Vicente Martinez
- Christos E. Kotselidis
- Grigorios Magklis
- Fernando Latorre
- Raul Martinez
- Josep M. Codina
- Enric Gibert Codina
- Crispin Gomez Requena
- Antonio Gonzelez
- Mirem Hyuseinova
- Pedro Lopez
- Marc Lupon
- Carlos Madriles
- Daniel Ortega
- Demos Pavlou
- Kyriakos A. Stavrou
- Georgios Tournavitis
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.