Managed instruction cache prefetching
US9811341B2 · kind B2 · utility
3Cited by
18References
5Claims
0Family size
Assignee
Inventors
- Kyriakos A. Stavrou
- Enric Gibert Codina
- Josep M. Codina
- Crispin Gomez Requena
- Antonio Gonzalez
- Mirem Hyuseinova
- Christos E. Kotselidis
- Fernando Latorre
- Pedro Lopez
- Marc Lupon
- Carlos Madriles Gimeno
- Grigorios Magklis
- Pedro Marcuello
- Alejandro Martinez Vicente
- Raul Martinez
- Daniel Ortega
- Demos Pavlou
- Georgios Tournavitis
- Polychronis Xekalakis
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.