Inventor · Peekskill, NY, US

Peter G. Ledermann

13Patents
12h-index
39Co-inventors
74Inventor score

Filing activity: Apr 29, 1986 → Dec 20, 1998

Most-cited inventions

PatentTitleAreaCited byStatus
US5117457A Tamper resistant packaging for information protection in electronic circuitry Electricity 253 Expired
US5343366A Packages for stacked integrated circuit chip cubes Electricity 112 Expired
US5028983A Multilevel integrated circuit packaging structures Electricity 59 Expired
US4814855A Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape Electricity 51 Expired
US4934309A Solder deposition system Electricity 43 Expired
US5189363A Integrated circuit testing system having a cantilevered contact lead probe pattern mounted on a flexible tape for interconnecting an integrated circuit to a tester Physics 43 Expired
US4970579A Integrated circuit package with improved cooling means Electricity 39 Expired
US4898117A Solder deposition system Electricity 25 Expired
US4881885A Dam for lead encapsulation Electricity 18 Expired
US5042708A Solder placement nozzle assembly Electricity 18 Expired
US5065932A Solder placement nozzle with inert cover gas and inert gas bleed Performing Operations; Transporting 17 Expired
US6278784A Intermittent errors in digital disc players Physics 17 Expired
US5130781A Dam for lead encapsulation Electricity 11 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.