Yu Wang
12Patents
4h-index
14Co-inventors
53Inventor score
Filing activity: Dec 28, 2005 → Aug 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8053315B2 | Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer | Electricity | 8 | Active |
| US7521332B2 | Resistance-based etch depth determination for SGT technology | Electricity | 4 | Active |
| US7932148B2 | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) | Electricity | 4 | Active |
| US7795108B2 | Resistance-based etch depth determination for SGT technology | Electricity | 4 | Active |
| US7492005B2 | Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes | Electricity | 3 | Active |
| US8021563B2 | Etch depth determination for SGT technology | Electricity | 1 | Active |
| US7632733B2 | Polysilicon control etch-back indicator | Electricity | 1 | Active |
| US7928507B2 | Polysilicon control etch-back indicator | Electricity | 1 | Active |
| US8471368B2 | Polysilicon control etch back indicator | Electricity | 0 | Active |
| US8884406B2 | Etch depth determination structure | Electricity | 0 | Active |
| US8193061B2 | Polysilicon control etch-back indicator | Electricity | 0 | Active |
| US12040234B2 | Semiconductor device and method for fabricating the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.