Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer
US8053315B2 · kind B2 · utility
8Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Oct 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.