Wafer-level packaging using wire bond wires in place of a redistribution layer

US10008469B2 · kind B2 · utility

Assignee

• Invensas LLC · US

Inventors

• Rajesh Katkar · Milpitas, US
• Tu Tam Vu · San Jose, US
• Bongsub Lee · Santa Clara, US
• Kyong-Mo Bang · San Jose, US
• Xuan Li · Santa Clara, US
• Long Huynh · Santa Clara, US
• Gabriel Z. Guevara · Gilroy, US
• Akash Agrawal · San Jose, US
• Willmar Subido · Garland, US
• Laura Wills Mirkarimi · Sunol, US

Key dates

• Filing date: Nov 21, 2016
• Grant date: Jun 26, 2018
• Expiry date: Nov 21, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/2064
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.