Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof
US10014316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.