Integration of super via structure in BEOL
US10020255B1 · kind B1 · utility
18Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.