Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method
US10090193B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0179
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit (IC) structure that incorporates stacked pair(s) of field effect transistors (FETs), where each stacked pair has a shared gate. The structure also includes an irregular-shaped buried interconnect that connects source/drain regions that are on opposite sides of the shared gate and at different levels (i.e., a lower FET's source/drain region on one side of the shared gate to an upper FET's source/drain region on the opposite side). Also disclosed is a method for forming the structure by forming, during different process stages, different sections of an irregular-shaped cavity (including sections that expose surfaces of the source/drain regions at issue and a section with sidewalls lined by a dielectric spacer) and filling the different sections with sacrificial material. When all of the sections are completed, the sacrificial material is selectively removed, thereby creating the irregular-shaped cavity. Then, the buried interconnect is formed within the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.