Methods and apparatuses having memory cells including a monolithic semiconductor channel
US10090317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Jul 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.