Low granularity coarse depth test efficiency enhancement
US10102609B1 · kind B1 · utility
4Cited by
0References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.