Patent · US Active

Layout effect characterization for integrated circuits

US10114914B2 · kind B2 · utility

0Cited by

1References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Martin Eckert · Metzingen, DE
Thomas Gentner · Eppelheim, DE
Jens Kuenzer · Eppelheim, DE
Antje Mueller · Eppelheim, DE
Thomas Strach · Wildberg, DE
Otto A. Torreiter · Echterdingen, DE

Key dates

Filing date	Nov 28, 2017
Grant date	Oct 30, 2018
Priority date	—
Expiry date	Nov 28, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.