Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

US10170389B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Steven K. Groothuis · Rowlett, US
• Jian Li · Boise, US
• Haojun Zhang · Clay, US
• Paul A. Silvestri · Meridian, US
• Xiao Li · Yardley, US
• Shijian Luo · Boise, US
• Luke England · Boise, US
• Brent Keeth · Boise, US
• Jaspreet S. Gandhi · Milpitas, US

Key dates

• Filing date: Aug 12, 2015
• Grant date: Jan 1, 2019
• Expiry date: Aug 12, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.