Semiconductor devices with robust low-k sidewall spacers and method for producing the same
US10192791B1 · kind B1 · utility
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5References
20Claims
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Key dates
| Filing date | Mar 6, 2018 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Mar 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8316
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.