Integrated circuit structure incorporating stacked field effect transistors
US10192819B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.