Method of forming a heterojunction semiconductor device having integrated clamping device
US10199373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.