Non-uniform gate oxide thickness for DRAM device

US10204909B2 · kind B2 · utility

Assignee

• Varian Semiconductor Equipment Associates, Inc. · US

Inventors

• Simon Ruffell · Lasów Chojnowskich, US
• Arvind Kumar · Beaverton, US
• Tristan Y. Ma · Lexington, US
• Kyu-Ha Shim · Andover, US
• John Hautala · Beverly, US
• Steven R. Sherman · Newton, US

Key dates

• Filing date: Dec 22, 2015
• Grant date: Feb 12, 2019
• Expiry date: Dec 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/26506
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.