Separate N and P fin etching for reduced CMOS device leakage

US10229910B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Isabel Cristina Chu · Mount Vernon, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Leigh Anne H. Clevenger · Rhinebeck, US
• Mona A. Ebrish · Albany, US
• Gauri Karve · Cohoes, US
• Fee Li Lie · Albany, US
• Deepika Priyadarshini · Guilderland, US
• Nicole Saulnier · Albany, US
• Indira Seshadri · Niskayuna, US

Key dates

• Filing date: May 12, 2017
• Grant date: Mar 12, 2019
• Expiry date: May 12, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.