Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

US10249490B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niti Goel · Portland, US
• Robert S. Chau · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Matthew V. Metz · Portland, US
• Niloy Mukherjee · Beaverton, US
• Nancy Zelick · Portland, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US
• Marko Radosavljevic · Portland, US
• Van H. Le · Portland, US
• Ravi Pillarisetty · Portland, US
• Sansaptak Dasgupta · Hillsboro, US

Key dates

• Filing date: Mar 14, 2017
• Grant date: Apr 2, 2019
• Expiry date: Mar 14, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02647
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.