Method of forming vertical field effect transistors with different gate lengths and a resulting structure

US10249538B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Yi Qi · Niskayuna, US
• Hsien-Ching Lo · Clifton Park, US
• Jianwei Peng · Daguantang, CN
• Wei Hong · Clifton Park, US
• Yanping Shen · Saratoga Springs, US
• Yongjun Shi · Clifton Park, US
• Hui Zang · Guilderland, US
• Ruilong Xie · Niskayuna, US
• Kangguo Cheng · Schenectady, US
• Tenko Yamashita · Schenectady, US
• Chun-Chen Yeh · Clifton Park, US

Key dates

• Filing date: Oct 3, 2017
• Grant date: Apr 2, 2019
• Expiry date: Oct 3, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/837
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.