Offstate parasitic leakage reduction for tunneling field effect transistors

US10249742B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Van H. Le · Portland, US
• Gilbert Dewey · Beaverton, US
• Benjamin Chu-Kung · Portland, US
• Ashish Agrawal · Hillsboro, US
• Matthew V. Metz · Portland, US
• Willy Rachmady · Beaverton, US
• Marc C. French · Forest Grove, US
• Jack T. Kavalieros · Portland, US
• Rafael Rios · Portland, US
• Seiyon Kim · Portland, US
• Seung Hoon Sung · Beaverton, US
• Sanaz K. Gardner · Portland, US
• James M. Powers · Paradise Valley, US
• Sherry R. Taft · Sherwood, US

Key dates

• Filing date: Jun 27, 2015
• Grant date: Apr 2, 2019
• Expiry date: Jun 27, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/751

Abstract

A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.