Process integration approach of selective tungsten via fill

US10256144B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• He Ren · San Jose, US
• Feiyue Ma · Santa Clara, US
• Yu Lei · Belmont, US
• Kai Wu · Palo Alto, US
• Mehul Naik · San Jose, US
• Zhiyuan Wu · Shanghai, CN
• Vikash Banthia · Los Altos, US
• Hua Al · Tracy, US

Key dates

• Filing date: Apr 26, 2017
• Grant date: Apr 9, 2019
• Expiry date: Apr 26, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/53257
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.