Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
US10256248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jun 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.