Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
US10269620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.