Molded package with chip carrier comprising brazed electrically conductive layers

US10283432B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mark Pavier · Felbridge, GB
• Wolfram Hable · Dresden, DE
• Angela Kessler · Regensburg, DE
• Michael Sielaff · Erwitte, DE
• Anton Pugatschow · Soest, DE
• Charles Rimbert-Riviere · Soest, DE
• Marco Sobkowiak · Warstein, DE

Key dates

• Filing date: Aug 24, 2018
• Grant date: May 7, 2019
• Expiry date: Aug 24, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.