Three-dimensional memory devices having a plurality of NAND strings
US10283452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Mar 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5329
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.