Semiconductor devices with post-probe configurability
US10283462B1 · kind B1 · utility
4Cited by
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10Claims
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Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.