Protection of high-K dielectric during reliability anneal on nanosheet structures
US10304936B2 · kind B2 · utility
4Cited by
8References
12Claims
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Key dates
| Filing date | May 4, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.