Asymmetric high-k dielectric for reducing gate induced drain leakage
US10367072B2 · kind B2 · utility
2Cited by
20References
13Claims
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Key dates
| Filing date | Oct 23, 2017 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Oct 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.