Method to form low resistance contact
US10374040B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2018 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Jun 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the manufacture of a semiconductor device, electrical interconnects are formed by depositing a dielectric layer over source/drain regions, and forming a continuous trench within the dielectric layer. The trench may traverse plural source/drain regions associated with adjacent devices. The electrical interconnects are thereafter formed by metallizing the trench and patterning the metallization layers to form discrete interconnects over and in electrical contact with respective source/drain regions. The source/drain interconnects exhibit a reentrant profile, which presents a larger contact area to later-formed conductive contacts than a conventional tapered profile, and thus improve manufacturability and yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.