Nanosheet field-effect transistors including a two-dimensional semiconducting material
US10388732B1 · kind B1 · utility
28Cited by
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20Claims
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Key dates
| Filing date | May 30, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.