Managing efficient selection of a particular processor thread for handling an interrupt
US10423550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2414
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.