Hierarchical depth buffer back annotaton

US10424107B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Vasanth Ranganathan · Cameron Park, US
• Saikat Mandal · Sacramento, US
• Saurabh Sharma · Santa Clara, US
• Vamsee Vardhan Chivukula · Folsom, US
• Karol A. Szerszen · Hillsboro, US
• Aleksander Olek Neyman · Gdańsk, PL
• Altug Koker · Cameron Park, US
• Prasoonkumar Surti · Folsom, US
• Abhishek R. Appu · Cameron Park, US
• Joydeep Ray · Folsom, US
• Art Hunter · Folsom, US
• Luis F. Cruz Camacho · Santa Clara, US
• Akshay R. Chada · Folsom, US

Key dates

• Filing date: Apr 1, 2017
• Grant date: Sep 24, 2019
• Expiry date: Apr 6, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.