Methods of forming merged source/drain regions on integrated circuit products
US10475904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2018 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Mar 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.