Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

US10522655B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• George R. Mulfinger · Gansevoort, US
• Ryan Sporer · Mechanicville, US
• Rick Carter · Saratoga Springs, US
• Peter Baars · Dresden, DE
• Hans-Jürgen Thees · Dresden, DE
• Jan Höntschel · Dresden, DE

Key dates

• Filing date: Sep 21, 2017
• Grant date: Dec 31, 2019
• Expiry date: Sep 21, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0128

Abstract

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.