Memory arrays, and methods of forming memory arrays

US10541252B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• David Daycock · Boise, US
• Richard J. Hill · Boise, US
• Christopher J. Larsen · Boise, US
• Woohee Kim · Meridian, US
• Justin B. Dorhout · Boise, US
• Brett D. Lowe · Boise, US
• John D. Hopkins · Meridian, US
• Qian Tao · Singapore, SG
• Barbara L. Casey · Meridian, US

Key dates

• Filing date: May 13, 2019
• Grant date: Jan 21, 2020
• Expiry date: May 13, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.