Patent · US Active

System and method for substrate wafer back side and edge cross section seals

US10546750B2 · kind B2 · utility

0Cited by

63References

5Claims

0Family size

Assignee

Vishay-Siliconix, LLC · US

Inventors

Hamilton Lu · Los Angeles, US
The-Tu Chau · San Jose, US
Kyle Terrill · Santa Clara, US
Deva Pattanayak · Saratoga, US
Sharon Shi · San Jose, US
Kuo-In Chen · Los Altos, US
Robert Xu · Fremont, US

Key dates

Filing date	Jan 5, 2016
Grant date	Jan 28, 2020
Priority date	—
Expiry date	Jan 5, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/668
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.