System and method for in-situ programming and read operation adjustments in a non-volatile memory
US10559370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Mar 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.