Semiconductor device including superlattice structures with reduced defect densities

US10566191B1 · kind B1 · utility

Assignee

• ATOMERA INCORPORATED · US

Inventors

• Keith Doran Weeks · Chandler, US
• Nyles Wynn Cody · Tempe, US
• Marek Hytha · Brookline, US
• Robert J. Mears · Wellesley, US
• Robert John Stephenson · Duxford, GB

Key dates

• Filing date: Aug 30, 2018
• Grant date: Feb 18, 2020
• Expiry date: Aug 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.