Critical methodology in vacuum chambers to determine gap and leveling between wafer and hardware components
US10599043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.