Method of forming a straight via profile with precise critical dimension control
US10622301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.