Array common source structures of three-dimensional memory devices and fabricating methods thereof
US10658379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28568
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a slit vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the slit; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.