Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions
US10665497B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Mar 13, 2017 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Mar 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.