Word line contact structure for three-dimensional memory devices and fabrication methods thereof
US10672711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.