Patent · US Active

Process integration approach of selective tungsten via fill

US10727119B2 · kind B2 · utility

1Cited by

9References

20Claims

0Family size

Assignee

Applied Materials, Inc. · US

Inventors

He Ren · San Jose, US
Feiyue Ma · Santa Clara, US
Yu Lei · Belmont, US
Kai Wu · Palo Alto, US
Mehul Naik · San Jose, US
Zhiyuan Wu · Shanghai, CN
Vikash Banthia · Los Altos, US
Hua Ai · Tracy, US

Key dates

Filing date	Jan 18, 2019
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Jan 18, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/53257
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.