Selective dielectric deposition to prevent gouging in MRAM
US10770653B1 · kind B1 · utility
3Cited by
8References
7Claims
0Family size
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Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.